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? 1 ? e02404 sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. ICX415AQ 22 pin dip (cer-dip) description the ICX415AQ is a diagonal 8mm (type 1/2) interline ccd solid-state image sensor with a square pixel array. progressive scan allows all pixel's signals to be output independently within approximately 1/50 second. this chip features an electronic shutter with variable charge-storage time which makes it possible to realize full-frame still image without a mechanical shutter. high resolution and high color reproductivity are achieved through the use of r, g, b primary color mosaic filters. further, high sensitivity and low dark current are achieved through the adoption of had (hole-accumulation diode) sensors. this chip is suitable for applications such as fa and surveillance cameras. features ? progressive scan allows individual readout of the image signals from all pixels. high vertical resolution still images without a mechanical shutter square pixel horizontal drive frequency: 29.5mhz r, g, b primary color mosaic filters on chip no voltage adjustments (reset gate and substrate bias are not adjusted.) high resolution, low dark current, high color reproductivity, high sensitivity continuous variable-speed shutter low smear excellent anti-blooming characteristics device structure interline ccd image sensor image size: diagonal 8mm (type 1/2) number of effective pixels: 782 (h) 582 (v) approx. 460k pixels total number of pixels: 823 (h) 592 (v) approx. 490k pixels chip size: 7.48mm (h) 6.15mm (v) unit cell size: 8.3m (h) 8.3m (v) optical black: horizontal (h) direction: front 3 pixels, rear 38 pixels vertical (v) direction: front 8 pixels, rear 2 pixels number of dummy bits: horizontal 19 vertical 5 substrate material: silicon optical black position (top view) diagonal 8mm (type 1/2) progressive scan ccd image sensor with square pixel for color cameras ? wfine ccd is trademark of sony corporation. represents a ccd adopting progressive scan, primary color filter and square pixel. 2 8 v h pin 1 pin 12 38 3
? 2 ? ICX415AQ block diagram and pin configuration (top view) pin no. symbol description pin no. symbol description 1 2 3 4 5 6 7 8 9 10 11 nc nc v 3 v 2 v 1 nc gnd nc v out c gg nc vertical register transfer clock vertical register transfer clock vertical register transfer clock gnd signal output output amplifier gate ? 1 12 13 14 15 16 17 18 19 20 21 22 v dd rg v l sub h 1 h 2 nc nc c sub subcir nc supply voltage reset gate clock protective transistor bias substrate clock horizontal register transfer clock horizontal register transfer clock substrate bias ? 2 supply voltage for the substrate voltage generation pin description ? 1 dc bias is applied within the ccd, so that this pin should be grounded externally through a capacitance of 1? or more. ? 2 dc bias is applied within the ccd, so that this pin should be grounded externally through a capacitance of 0.1? or more. note) note) : photo sensor horizontal register vertical register 8 7 6 5 4 3 2 1 nc gnd nc v 1 v 2 v 3 nc nc 17 18 19 20 21 22 h 2 16 h 1 15 sub 11 10 9 nc c gg v out 14 v l 13 rg 12 v dd nc nc c sub subcir nc r r r r r r r r g g g g g g g g g g g g g g b b b b b b
? 3 ? ICX415AQ absolute maximum ratings item v dd , v out , c gg , subcir ? gnd v dd , v out , c gg , subcir ? sub v 1 , v 2 , v 3 ? gnd v 1 , v 2 , v 3 ? sub substrate clock sub ? gnd supply voltage clock input voltage voltage difference between vertical clock input pins voltage difference between horizongal clock input pins h 1 , h 2 ? v 3 h 1 , h 2 ? gnd h 1 , h 2 ? sub v l ? sub v 2 , v 3 ? v l rg ? gnd v 1 , h 1 , h 2 , gnd ? vl storage temperature performance guarantee temperature operating temperature ? 0.3 to +55 ? 0.3 to +18 ? 55 to +10 ? 15 to +20 to +10 to +15 to +17 ? 16 to +16 ? 10 to +15 ? 55 to +10 ? 65 to +0.3 ? 0.3 to +27.5 ? 0.3 to +22.5 ? 0.3 to +17.5 ? 30 to +80 ? 10 to +60 ? 10 to +75 v v v v v v v v v v v v v v c c c ? 1 ratings unit remarks ? 1 +27v (max.) when clock width < 10?, clock duty factor < 0.1%. +16v (max.) is guaranteed for power-on and power-off.
? 4 ? ICX415AQ bias conditions ? 1 v l setting is the v vl voltage of the vertical transfer clock waveform, or the same voltage as the v l power supply for the v driver should be used. ? 2 indications of substrate voltage setting value set subcir pin to open when applying a dc bias the substrate clock pin. adjust the substrate voltage because the setting value of the substrate voltage is indicated on the back of image sensor by a special code when applying a dc bias the substrate clock pin. v sub code ? two characters indication integer portion decimal portion the integer portion of the code and the actual value correspond to each other as follows. dc characteristics supply current item i dd symbol 7.0 min. unit remarks typ. max. ma supply voltage protective transistor bias substrate clock reset gate clock item v dd v l sub rg symbol 15.0 ? 1 ? 2 ? 3 min. v unit remarks typ. max. 14.55 15.45 9.0 4.0 a 5 c 6 d 7 e 8 f 9 g 10 h 11 j 12 integer portion of code value [example] "a5" v sub = 5.5v ? 3 do not apply a dc bias to the reset gate clock pins, because a dc bias is generated within the ccd.
? 5 ? ICX415AQ clock voltage conditions readout clock voltage vertical transfer clock voltage horizontal transfer clock voltage reset gate clock voltage substrate clock voltage item v vt v vh02 v vh1 , v vh2 , v vh3 v vl1 , v vl2 , v vl3 v vl1 , v vl2 , v vl3 v 1 , v 2 , v 3 | v vl1 ? v vl3 | v vhh v vhl v vlh v vll v h v hl v cr v rg v rglh ? v rgll v rgl ? v rglm v sub symbol 14.55 ? 0.05 ? 0.2 ? 7.8 ? 8.0 6.8 4.75 ? 0.05 0.8 4.5 21.5 min. 15.0 0 0 ? 7.5 ? 7.5 7.5 5.0 0 2.5 5.0 22.5 ty p . 15.45 0.05 0.05 ? 7.2 ? 7.0 8.05 0.1 0.5 0.5 0.5 0.5 5.25 0.05 5.5 0.8 0.5 23.5 max. unit 1 2 2 2 2 2 2 2 2 2 2 3 3 3 4 4 4 5 waveform diagram v vh = v vh02 v vl = (v vl1 + v vl3 )/2 (during 29.5mhz) v vl = (v vl1 + v vl3 )/2 (during 14.75mhz) high-level coupling high-level coupling low-level coupling low-level coupling cross-point voltage low-level coupling low-level coupling remarks v v v v v v v v v v v v v v v v v v
? 6 ? ICX415AQ clock equivalent circuit constants c v1 c v2 c v3 c v12 c v23 c v31 c h1 , c h2 c hh c rg c sub r 1 , r 2 r 3 r gnd r h1 , r h2 r rg symbol capacitance between vertical transfer clock and gnd capacitance between vertical transfer clocks capacitance between horizontal transfer clock and gnd capacitance between horizontal transfer clocks capacitance between reset gate clock and gnd capacitance between substrate clock and gnd vertical transfer clock series resistor vertical transfer clock ground resistor horizontal transfer clock series resistor reset gate clock series resistor item min. 3900 3300 3300 2200 2200 1800 47 30 6 390 27 22 100 16 39 ty p. max. pf pf pf pf pf pf pf pf pf pf ? ? ? ? ? unit remarks horizontal transfer clock equivalent circuit reset gate clock equivalent circuit vertical transfer clock equivalent circuit v 3 r gnd c v3 c v1 c v2 c v23 c v31 c v12 r 3 r 1 r 2 v 2 v 1 h 1 h 2 c h1 c h2 c hh r h2 r h1 r rg c rg
? 7 ? ICX415AQ drive clock waveform conditions (1) readout clock waveform (2) vertical transfer clock waveform 100% 90% 10% 0% tr tf 0v twh m 2 m v vt note) readout clock is used by composing vertical transfer clocks v 2 and v 3 . v vlh v vl03 v vll v vh = v vh02 v vl = (v vl01 + v vl03 )/2 v vl3 = v vl03 v vl v vh1 v vhh v vh v vhl v vlh v vl1 v vl01 v vl v vll v vh3 v vhh v vh v vhl v vlh v vl2 v vll v vl v vh v vhh v vh02 v vh2 v vhl v v1 = v vh1 ? v vl01 v v2 = v vh02 ? v vl2 v v3 = v vh3 ? v vl03 v 1 v t v 2 v 3
? 8 ? ICX415AQ h 2 h 1 two twh tr tf 90% 10% twl v cr v hl v h v h 2 rg waveform v rglh v rgll v rglm v rgh tr tf twh twl v rgl point a v rg v sub (a bias generated within the ccd) 100% 90% 10% 0% tr tf twh m 2 m v sub (3) horizontal transfer clock waveform cross-point voltage for the h 1 rising side of the horizontal transfer clocks h 1 and h 2 waveforms is v cr . the overlap period for twh and twl of horizontal transfer clocks h 1 and h 2 is two. (4) reset gate clock waveform v rglh is the maximum value and v rgll is the minimum value of the coupling waveform during the period from point a in the above diagram until the rising edge of rg. in addition, v rgl is the average value of v rglh and v rgll . v rgl = (v rglh + v rgll )/2 assuming v rgh is the minimum value during the interval twh, then: v rg = v rgh ? v rgl negative overshoot level during the falling edge of rg is v rglm . (5) substrate clock waveform h 1 , h 2 rg sub
? 9 ? ICX415AQ ? 1 the overlap period of twh and twl of horizontal transfer clocks h 1 and h 2 is two. clock switching characteristics (horizontal drive frequency: 29.5mhz) min. twh typ. max. min. typ. max. min. typ. max. min. typ. max. twl tr tf 2.3 9.5 9.5 4 0.7 2.5 12.0 12.0 7 0.8 9.5 9.5 12.0 12.0 22 0.5 5.0 5.0 2 7.5 7.5 0.5 15 0.5 5.0 5.0 3 250 7.5 7.5 0.5 unit ? ns ns ns ? remarks during readout when using cxd3400n tf tr ? 2ns during drain charge item readout clock vertical transfer clock horizontal transfer clock reset gate clock substrate clock symbol v t v 1 , v 2 , v 3 h 1 h 2 rg sub min. two typ. max. 7.5 9.5 unit ns remarks item horizontal transfer clock symbol h 1 , h 2 ? 1 clock switching characteristics (horizontal drive frequency: 14.75mhz) min. twh typ. max. min. typ. max. min. typ. max. min. typ. max. twl tr tf 4.6 18 21 11 1.4 5.0 23 26 14 1.6 21 18 26 23 49 0.5 10 10 2 17.5 15 0.5 15 0.5 10 10 2 350 17.5 15 0.4 unit ? ns ns ns ? remarks during readout when using cxd3400n tf tr ? 2ns during drain charge item readout clock vertical transfer clock horizontal transfer clock reset gate clock substrate clock symbol v t v 1 , v 2 , v 3 h 1 h 2 rg sub min. two typ. max. 20 24 unit ns remarks item horizontal transfer clock symbol h 1 , h 2 ? 1
? 10 ? ICX415AQ note) all image sensor characteristic data noted above is for operation in 1/50s progressive scan mode. image sensor characteristics (ta = 25 c) item g sensitivity sensitivity comparison saturation signal smear video signal shading uniformity between video signal channels dark signal dark signal shading lag symbol sg rr rb vsat sm shg ? srg ? sbg vdt ? vdt lag min. 570 0.4 0.3 375 ty p . 720 0.55 0.45 ? 100 max. 940 0.7 0.6 ? 92 25 8 8 2 1 0.5 unit mv mv db % % % mv mv % measurement method 1 1 1 2 3 4 5 5 6 7 8 remarks 1/25s accumulation conversion value ta = 60 c zone 0 ta = 60 c ta = 60 c zone definition of video signal shading measurement system ccd c.d.s s/h s/h amp ccd signal output [ ? a] gr/gb channel signal output [ ? b] r/b channel signal output [ ? c] gr/gb r/b note) adjust the amplifier gain so that the gain between [ ? a] and [ ? b], and between [ ? a] and [ ? c] equals 1. 66 2 2 ignored region effective pixel region zone 0 782 (h) 582 (v)
? 11 ? ICX415AQ image sensor characteristics measurement method measurement conditions (1) in the following measurements, the device drive conditions are at the typical values of the bias and clock voltage conditions. (2) in the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical black level (ob) is used as the reference for the signal output, which is taken as the value of the gr/gb channel signal output or the r/b channel signal output of the measurement system. (2) in the following measurements, this image sensor is operated in 1/50s all pixels progressive scan mode. color coding of this image sensor & readout the primary color filters of this image sensor are arranged in the layout shown in the figure on the left (bayer arrangement). gr and gb denote the g signals on the same line as the r signal and the b signal, respectively. gb b gb b rgrrgr gb b gb b rgrrgr horizontal register color coding diagram all pixels' signals are output successively in a 1/50s period. r signal and gr signal lines and gb signal and b signal lines are output sequentially.
? 12 ? ICX415AQ 1. progressive scan mode in this mode, all pixel signals are output in non-interlace format in 1/50s. all pixel signals within the same exposure period are read out simultaneously, making this mode suitable for high resolution image capturing. image sensor readout mode the diagram below shows the output methods for the following two readout modes. (1) progressive scan mode 2. center scan mode this is the center scan mode using the progressive scan method. the undesired portions are swept by vertical register high-speed transfer, and the picture center portion is cut out. there are the mode (100 frames/s) which outputs 264 lines of an output line portion, and the mode (200 frames/s) which outputs 88 lines. (2) center scan mode undesired portions (swept by vertical register high-speed transfer) picture center cut-out portion v out r r r g g g g g b b
? 13 ? ICX415AQ definition of standard imaging conditions (1) standard imaging condition i : use a pattern box (luminance: 706cd/m 2 , color temperature of 3200k halogen source) as a subject. (pattern for evaluation is not applicable.) use a testing standard lens with cm500s (t = 1.0mm) as an ir cut filter and image at f5.6. the luminous intensity to the sensor receiving surface at this point is defined as the standard sensitivity testing luminous intensity. (2) standard imaging condition ii : image a light source (color temperature of 3200k) with a uniformity of brightness within 2% at all angles. use a testing standard lens with cm500s (t = 1.0mm) as an ir cut filter. the luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm. 1. g sensitivity, sensitivity comparison set to the standard imaging condition i . after setting the electronic shutter mode with a shutter speed of 1/100s, measure the signal outputs (v gr , v gb , v r and v b ) at the center of each gr, gb, r and b channel screen, and substitute the values into the following formulas. v g = (v gr + v gb )/2 sg = v g [mv] rr = v r /v g rb = v b /v g 2. saturation signal set to the standard imaging condition ii . after adjusting the luminous intensity to 20 times the intensity with the average value of the gr signal output, 120mv, measure the minimum values of the gr, gb, r and b signal outputs. 3. smear set to the standard imaging condition iii . with the lens diaphragm at f5.6 to f8, first adjust the average value of the gr signal output to 120mv. measure the average values of the gr signal output, gb signal output, r signal output and b signal output (gra, gba, ra, ba), and then adjust the luminous intensity to 500 times the intensity with the average value of the gr signal output, 120mv. after the readout clock is stopped and the charge drain is executed by the electronic shutter at the respective h blankings, measure the maximum value (vsm [mv]) independent of the gr, gb, r and b signal outputs, and substitute the values into the following formula. sm = 20 log ( vsm ? ) [db] (1/10v method conversion value) 1 10 1 500 gra + gba + ra + ba 4 100 25
? 14 ? ICX415AQ 4. video signal shading set to the standard imaging condition ii . with the lens diaphragm at f5.6 to f8, adjusting the luminous intensity so that the average value of the gr signal output is 120mv. then measure the maximum value (grmax [mv]) and minimum value (grmin [mv]) of the gr signal output and substitute the values into the following formula. shg = (grmax ? grmin)/120 100 [%] 5. unifoemity between video signal channels after measuring 4, measure the maximum (rmax [mv]) and minimum (rmin [mv]) values of r signal, and the maximum (bmax [mv]) and minimum (bmin [mv]) values of b signal. substitute the values into the following formula. ? srg = (rmax ? rmin )/120 100 [%] ? sbg = (bmax ? bmin )/120 100 [%] 6. dark signal measure the average value of the signal output (vdt [mv]) with the device ambient temperature of 60 c and the device in the light-obstructed state, using the horizontal idle transfer level as a reference. 7. dark signal shading after measuring 6, measure the maximum (vdmax [mv]) and minimum (vdmin [mv]) values of the dark signal output and substitute the values into the following formula. ? vdt = vdmax ? vdmin [mv] 8. lag adjust the gr signal output value generated by the strobe light to 120mv. after setting the strobe light so that it strobes with the following timing, measure the residual signal amount (vlag). substitute the value into the following formula. lag = (vlag/120) 100 [%] light gr signal output 120mv vlag(lag) vd v2 strobe light timing output
? 15 ? ICX415AQ drive circuit xsub xv3 xsg3 xv2 xsg2 xv1 h 2 h 1 rg ccd out ? 7.5v 0.1 0.1 0.1 1/10v 0.1 0.01 2200p 0.1 3.3/16v 3.3/20v 0.1 1/35v 100k 1m 4.7k 2sc4250 1 2 3 4 5 6 7 8 22 21 20 19 18 17 16 15 9 10 11 14 13 12 icx415 (bottom view) nc nc v 3 v 2 v 1 nc gnd nc v out c gg nc nc subcir c sub nc nc h 2 h 1 sub v l rg v dd 11 12 13 14 15 16 17 18 19 20 10 9 8 7 6 5 4 3 2 1 cxd3400n 15v 3.3v
? 16 ? ICX415AQ spectral sensitivity characteristics (includes lens characteristics, excludes light source characteristics) 0 400 450 500 550 600 650 700 0.2 0.4 0.6 b g r 0.8 1.0 relative response wave length [nm]
? 17 ? ICX415AQ drive timing chart (vertical sync) progressive scan mode 582 1 2 6 5 582 1 2 7 8 1 2 3 4 6 5 7 8 1 2 3 4 1 2 3 vd hd "a" v1 v2 v3 out 625 598 1 7 596 598 1 625 7
? 18 ? ICX415AQ drive timing chart (vertical sync "a" enlarged) progressive scan mode/center scand mode "a" enlarged 16 16 16 16 16 16 16 16 16 16 16 16 74 74 627 701 h1 v1 v2 v3
? 19 ? ICX415AQ drive timing chart (horizontal sync) progressive scan mode 1 1 48 48 1 48 16 11 1 32 16 16 148 32 1 1 6 1 1 123 944 1 1 4 42 1 163 166 144 138 96 102 1 19 clk h1 h2 shp shd v1 v2 v3 sub rg 57
? 20 ? ICX415AQ drive timing chart (vertical sync) center scan mode 1 422 423 160 161 1 422 423 1 vd hd "d" "b" "c" v1 v2 v3 out "a" "d" "b" "a" 291 290 311 310 312 1 2 3 4 5 6 7 8 23 24 27 291 290 311 310 312 1 2 3 4 5 6 7 8
? 21 ? ICX415AQ drive timing chart (horizontal sync) center scan mode 1 (frame shift) ("b") 16 16 16 16 #1 16 16 16 16 16 16 16 16 h1 h2 v1 v2 v3 #166 42 102 16048 bits = 17h
? 22 ? ICX415AQ drive timing chart (horizontal sync) center scan mode 1 (high-speed sweep) ("d") 16 16 16 16 #1 16 16 16 16 16 16 16 16 h1 h2 v1 v2 v3 #194 42 102 18880 bits = 20h
? 23 ? ICX415AQ drive timing chart (vertical sync) center scan mode 2 334 335 248 249 1 334 335 1 vd hd "d" "b" "c" v1 v2 v3 out "a" "d" "b" "a" 124 123 155 156 1 2 3 4 5 6 7 8 36 33 32 154 124 123 155 156 1 2 3 4 5 6 7 8 154
? 24 ? ICX415AQ drive timing chart (horizontal sync) center scan mode 2 (frame shift) ("b") 16 16 16 16 #1 16 16 16 16 16 16 16 16 h1 h2 v1 v2 v3 #254 42 102 24544 bits = 26h
? 25 ? ICX415AQ drive timing chart (horizontal sync) center scan mode 2 (high-speed sweep) ("d") 16 16 16 16 #1 16 16 16 16 16 16 16 16 h1 h2 v1 v2 v3 #299 42 102 29264 bits = 31h
? 26 ? ICX415AQ notes on handling 1) static charge prevention ccd image sensors are easily damaged by static discharge. before handling be sure to take the following protective measures. a) either handle bare handed or use non-chargeable gloves, clothes or material. also use conductive shoes. b) when handling directly use an earth band. c) install a conductive mat on the floor or working table to prevent the generation of static electricity. d) ionized air is recommended for discharge when handling ccd image sensor. e) for the shipment of mounted substrates, use boxes treated for the prevention of static charges. 2) soldering a) make sure the package temperature does not exceed 80 c. b) solder dipping in a mounting furnace causes damage to the glass and other defects. use a 30w soldering iron with a ground wire and solder each pin in less than 2 seconds. for repairs and remount, cool sufficiently. c) to dismount an image sensor, do not use a solder suction equipment. when using an electric desoldering tool, use a thermal controller of the zero cross on/off type and connect it to ground. 3) dust and dirt protection image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and dirt. clean glass plates with the following operation as required, and use them. a) perform all assembly operations in a clean room (class 1000 or less). b) do not either touch glass plates by hand or have any object come in contact with glass surfaces. should dirt stick to a glass surface, blow it off with an air blower. (for dirt stuck through static electricity ionized air is recommended.) c) clean with a cotton bud and ethyl alcohol if the grease stained. be careful not to scratch the glass. d) keep in a case to protect from dust and dirt. to prevent dew condensation, preheat or precool when moving to a room with great temperature differences. e) when a protective tape is applied before shipping, just before use remove the tape applied for electrostatic protection. do not reuse the tape. 4) installing (attaching) a) remain within the following limits when applying a static load to the package. do not apply any load more than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to limited portions. (this may cause cracks in the package.) b) if a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the ceramic portions. therefore, for installation, use either an elastic load, such as a spring plate, or an adhesive. 39n lower ceramic upper ceramic compressive strength low melting point glass 29n shearing strength 29n tensile strength 0.9nm torsional stregth
? 27 ? ICX415AQ c) the adhesive may cause the marking on the rear surface to disappear, especially in case the regulated voltage value is indicated on the rear surface. therefore, the adhesive should not be applied to this area, and indicated values should be transferred to other locations as a precaution. d) the notch of the package is used for directional index, and that can not be used for reference of fixing. in addition, the cover glass and seal resin may overlap with the notch of the package. e) if the leads are bent repeatedly and metal, etc., clash or rub against the package, the dust may be generated by the fragments of resin. f) acrylate anaerobic adhesives are generally used to attach ccd image sensors. in addition, cyano- acrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives. (reference) 5) others a) do not expose to strong light (sun rays) for long periods, as color filters will be discolored. when high luminous objects are imaged with the exposure level controlled by the electronic iris, the luminance of the image-plane may become excessive and discoloring of the color filter will possibly be accelerated. in such a case, it is advisable that taking-lens with the automatic-iris and closing of the shutter during the power- off mode should be properly arranged. for continuous using under cruel condition exceeding the normal using condition, consult our company. b) exposure to high temperature or humidity will affect the characteristics. accordingly avoid storage or usage in such conditions. c) brown stains may be seen on the bottom or side of the package. but this does not affect the ccd characteristics.
? 28 ? ICX415AQ sony corporation package outline unit: mm 0.7 3 14.6 1.27 0.46 0.3 0.69 4.0 ?0.3 3.4 ?0.3 1.27 15.1 ?0.3 7.55 9.0 18.0 ?0.4 17.6 22 pin dip (600mil) b v h 22 12 11 1 2-r0.7 22 12 11 1 a ' (for the 1st.pin only) 0.3 m 1. " a " is the center of the effective image area. 2 . the two points " b " of the package are the horizontal reference. the point " b " of the package is the vertical reference. 3 . the bottom " c " of the package is the height reference. 4 . the center of the effective image area,relative to " b " and " b' " is ( h, v) = (9.0, 7.55) 0.15mm 5 . the rotation angle of the effective image area relative to h and v is ?1? 6 . the height from bottom " c " to the effective image area is 1.41 ?0.15mm 7 . the tilt of the effective image area relative to the bottom " c " is less than 60? . 8 . the thickness of the cover glass is 0.75mm,and the refractive index is 1.5. 9 . the notches on the bottom must not be used for reference of fixing. 0.7 3 11.55 3 0.55 b ~ ~ ~ 0.25 15.24 c 0 ? to 9? package material lead treatment lead material package mass drawing number cer-dip tin plating 42 alloy 2.60g as-b15-01(e)

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